This invention relates to a method of manufacturing a metal-semiconductor field effect transistor and in particular to the method of forming the gate electrode for such transistors.
Fabrication of the metal semiconductor field effect transistor (MESFET, or more commonly, a FET) involves forming drain, source, and gate electrodes on the surface of a semiconductor substrate. Ohmic contacts are generally used for the drain and source electrodes whereas a rectifying, Schottky barrier metal system is used for the gate electrode.
Current techniques used in fabricating gate electrodes attempt to achieve short gate lengths, low electrical resistance along the width of the gate, and the option to pre-etch the semiconductor before gate metallization is done. Also it is desirable that minimal stress be induced into the semiconductor by the gate metallization. Furthermore, it is desirable that the gate structure be compatible with self-aligning techniques to reduce gate-source and gate-drain electrode spacings. Current techniques used in fabricating gate electrodes may include some but do not include all of these features.
A common technique currently used involves lifting evaporated metal with a previously defined photoresist pattern off of the semiconductor surface, with only the gate electrode remaining. Here short gate lengths can be obtained and the semiconductor can be etched before metal deposition, but the electrical resistance along the gate width is severely limited by the thin layer of metal that can be lifted by such a process. One example of this technique is disclosed in U.S. Pat. No. 4,048,712, although the gate structure described in that patent is not particularly thin. In the structure described in the foregoing patent, self-alignment of the source and drain metallization is accomplished; however, this feature is generally not present in other prior art processes of this type.
Another common technique involves depositing a Schottky barrier metal over the entire semiconductor surface, photolithographically opening gate regions, electrolytically plating gold into these openings, and removing the photoresist and bare metal away from the area surrounding the gate electrode. This procedure, although providing short gate lengths and relatively low gate resistance, cannot be used with pre-etching techniques. Unless the gold is allowed to be plated over the top of the photoresist, a poorly defined procedure, this technique of gate formation also results in a structure which is not compatible with self-aligning procedures for the source and drain metallization.